1. Technical Field
Embodiments of the present invention relate to programmable logic devices (PLDs) that include programmable shift registers. More particularly, embodiments of the present invention relate to field programmable gate arrays (FPGAs) that include look up tables (LUTs) configured to form shift registers, the structures referred to as shift register LUTs (SRLs).
2. Related Art
An FPGA is an integrated circuit chip which includes components such as programmable input/output buffers (IOBs), configurable logic blocks (CLBs), block random access memory (BRAMs) and a programmable interconnect circuitry for interconnecting the IOBs, CLBs and BRAMs. The FPGAs further include SRAM configuration memory cells that can be programmed to configure the logic in the IOBs, CLBs and BRAMs. The SRAM configuration memory cells are typically programmed at startup of the FPGA, but can be reprogrammed using a partial reconfiguration process during operation of the FPGA by programming frames or a number of columns of the SRAM memory cells at a time.
The CLBs include a number of LUTs typically made up of components such as multiplexers and SRAM memory cells. At configuration, a bitstream is provided to program the individual SRAM memory cells to set the state of each LUT with a desired function by writing the truth table of the desired function to the individual SRAM memory cells. Each LUT implements a logic function with n inputs that select an output depending on how the SRAM memory cells are programmed or configured. Logic functions may use all n inputs to the logic element or may use only a subset thereof. A few of the possible logic functions that an LUT can implement are: AND, OR, XOR, NAND, NOR, XNOR and mixed combinations of these functions.
FIG. 1 shows one SRAM memory cell structure for use in a LUT. The memory cell 2 includes a latch 4 formed by series inverters that are programmed by applying the value to the source-drain path of a transistor 6 on the data input bit line, “Data,” and strobing the corresponding gate with an address “Address,” or word line signal. Although this architecture uses five transistors, other known SRAM configurations, e.g., six transistor static memory cells, also are appropriate choices for implementing the memory cells of the LUT. As shown in FIG. 1, inverter 8 may be included to increase the drive of memory cell 2.
FIG. 2 shows an alternative embodiment to memory cell structure of a LUT of FIG. 1 with the memory cell modified to include an additional programming transistor 7 to provide complementary programming data inputs BIT and BITB, as well as an additional output inverter 9 to provide complementary outputs Q and QB. Components carried over from FIG. 1 into subsequent figures are similarly labeled in FIG. 2, as will be components carried forward in subsequent drawings.
FIG. 3 shows a block diagram of components making up a two input LUT that includes four memory cells 10 and drivers 11 connecting to a multiplexer 12, each memory cell 10 and driver 11 with memory cells having a structure such as shown in either of FIG. 1 or FIG. 2. After configuration of the memory cells 10, to use a LUT of FIG. 2 the input lines act as address lines I0 and I1 which select a corresponding memory cell 10 in the LUT. For example, a LUT configured to implement a two-input NAND gate would output the corresponding value {1, 1, 1, or 0} contained in the one of the four memory cells 10 corresponding to the current input pair {00, 01, 10, 11}, respectively. This selection is performed by a decoding multiplexer 12 which selects a memory cell 10 on the basis of the logic levels of the input lines I1 and I1. The multiplexer 12 propagates a value stored in one of the memory cells 10 to an output OUT of the lookup table as selected by the input signals I0 and I1.
FIG. 4 illustrates circuitry that can be provided with the memory cell 20 of either FIGS. 1 and 2 to create a shift register mode, enabling a value to be shifted from a proceeding memory cell into a subsequent cell in a LUT to form a SRL. The additional circuitry includes pass transistors 14 and 22 to shift data in and out to set the state of latch 4. The pass transistor 14 provides a data signal to latch 4 and has a source-drain path connecting to the QB input of latch 4. The pass transistor 22 is connected between latch 4 and output inverter 8 to apply the state of latch 4 to a subsequent memory cell. The pass transistor 14 receives a gate shift signal SHIFT1 in conjunction with a gate shift signal SHIFT2 applied to pass transistor 22. The shift signal SHIFT1 is provided 180 degrees out of phase with the shift signal SHIFT2 to accomplish shifting data through a register formed by a number of chained memory cells, such as the cell shown in FIG. 4. An inverter 24, similar to inverter 8 following memory cell 20, is attached to the preceding memory cell from cell 20 to shift in data. The inverter 24 is designed to overpower the inverters of latch 4 so that values can be shifted between adjacent memory cells. Therefore, the current value stored in each memory cell is overwritten by the output of the previous memory cell. Interconnected memory cells as shown in FIG. 4 can be used to form the memory cells of a LUT connected as shown in FIG. 3 to form a SRL.
FIG. 5 illustrates LUT memory cells configured to form a shift register, with complementary data being shifted in and out. Two memory cells 30 and 32 are shown connected together. The memory cells 30 and 32 each include the latch 4, and a first pass transistor 14, similar to the cell of FIG. 4. The first pass transistor 14 has a source-drain path connected to the Q output of the latch 4, while an additional pass transistor 15 is added to the memory cells 30 and 32 in FIG. 6 with a source-drain path connecting a previous memory cell output to the QB input of latch 4. The transistors 14 and 15, thus, provide complementary inputs, and both have a gate receiving the SHIFT1 input signal. Further in FIG. 5, a pass transistor 23 is added in addition to pass transistor 22 to provide complementary outputs in response to a gate signal SHIFT2. Pass transistors 22 and 23 in combination with latches 8 and 9 form a dynamic latch.
The circuitry shown in FIGS. 1-5, and described herein are generally described in U.S. Pat. No. 5,889,413 to Bauer, entitled “Lookup Tables Which Double As Shift Registers,” and incorporated by reference herein in its entirety.
SRLs provide general purpose shift register structures on FPGAs and are widely used in FSM-based controls, delay pipelines, FIR/IIR filters, etc. For the specific case of SRL, efficient implementation hinges upon re-use of configuration resources. For SRAM-based FPGAs, configuration is typically expressed in terms of SRAM-cell contents. Unfortunately, these cells are not usually bit-addressable during either initial configuration or partial reconfiguration. Thus, any associated programming operations are typically performed using the smallest addressable region, which may be a frame or multiple columns of bits. To maintain a state management control of changes to individual memory cell bits requires storage of data for all the frames that must be reprogrammed at one time. Programming operations are, thus, typically time consuming, even when partial reconfiguration of less than all frames is performed.